Jon Wolfe

pm-cpu also reported, and expected DIFFS blessed

@cbegeman - done

@cbegeman -- OK, I ran the scripts but all they came up with was a couple of lines in the namelist definitions. I you still have this issue, can you...

That looks like a real fail -- let me take a peek. OK, the mesh should be SOwISC12to30E3r3 and not SOwISC12to60E3r3

@cbegeman -- is this still NCC? For all configurations?

testing shows non-BFB baseline results for: SMS_D_Ld1.ne30pg2_r05_IcoswISC30E3r5.WCYCL1850.chrysalis_intel.allactive-wcprod

Test merge passes: * ERS.ne4pg2_oQU480.WCYCL1850NS.chrysalis_intel * SMS_D_Ld1.ne30pg2_r05_IcoswISC30E3r5.WCYCL1850.chrysalis_intel.allactive-wcprod * ERP_Ld3.ne30pg2_r05_IcoswISC30E3r5.WCYCL1850.chrysalis_intel.allactive-pioroot1 * ERS_Ld5.T62_oQU120.CMPASO-NYF.chrysalis_intel * ERS_Ld5.TL319_oQU240wLI_ais8to30.GMPAS-JRA1p5-DIB-PISMF-DIS.chrysalis_intel.mpaso-ocn_glcshelf * ERS_Ld5.TL319_oQU240wLI_ais8to30.GMPAS-JRA1p5-DIB-PISMF-SIS.chrysalis_intel.mpaso-ocn_glcshelf * ERS_Ld5.T62_oQU240wLI.GMPAS-DIB-IAF-DISMF.chrysalis_intel.C.20250327_114302_nmarmq * ERS_Ld5.T62_oQU240wLI.GMPAS-DIB-IAF-PISMF.chrysalis_intel * PEM_Ln5.T62_oQU240wLI.GMPAS-DIB-IAF-DISMF.chrysalis_intel * PEM_Ln5.T62_oQU240wLI.GMPAS-DIB-IAF-PISMF.chrysalis_intel * PET_Ln5.T62_oQU240wLI.GMPAS-DIB-IAF-DISMF.chrysalis_intel * PET_Ln5.T62_oQU240wLI.GMPAS-DIB-IAF-PISMF.chrysalis_intel with expected NML...

With the latest commit, the failing test now passes. Because it was likely a threading issue, I ran it multiple times to be sure it was fixed -- it has...

@xylar - have your comments been resolved for this PR?

Shows expected baseline DIFFs for: * ERP_Ld3.ne30pg2_r05_IcoswISC30E3r5.WCYCL1850.chrysalis_intel.allactive-pioroot1 merged to next