vhdl-style-guide
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jeremiah-c-leary
Resiliance to malformed VHDL
What is your question? Sometimes I run VSG against code that does not compile i.e. it has VHDL syntax errors. VSG tends to fall over in a heap. Should this happen? Are there not traps somewhere so VSG can fail gracefully?
I would think that is possible, after all vcom does not stop at the first error.
Currently my parser will stop if there is a syntax error, but a syntax error is just something missing. I might be able to continue parsing and just skip the missing element.
No guarantee the rest could be parsed though.
It might give false results.
Maybe just analyze up to the syntax error?
When malformed VHDL is processed, I'd like VSG to report this rather than some obscure traceback error