Iztok Jeras

Hi, Based on your description I agree, synthesizing generated networks would not make too much sense, except maybe for very large networks which already passed a few rounds of SW...

Following the standard details posted by @diogratia (could you check, if this shanged in VHDL-2019?), it appears the GHDL behavior is correct and Questa would have to report an error....

For the other error it will take me more time to bisect the code, and it will be a separate issue.

Since this example did not output an error in Questa, I tried it on other simulators on Edaplayground and got the following results: https://www.edaplayground.com/x/SPWm | simulator | result | |---|---|...

There are probably a few other build systems with the same issue (same file name different directory), which already have a solution. Historically C compiler object files were placed in...

Sorry, I did not mean to point to a specific argument. I just wanted to point out there are other tools with similar issues, and they might have a well...

I would just like to mention a workaround. I never noticed this issue, since I have not used _array literals_ with replication yet, instead I would write `LST[LEN] = '{default:...

From a clean clone, and following instructions in the README, **I got a working build**. The steps I performed: ``` git clone [email protected]:chipsalliance/synlig.git sudo apt install -y gcc-11 g++-11 build-essential...

Having the same issue, as per above comments I used the following CLI to install `d38859f` (also tried `dev` but it had the same issue): ``` pip3 install git+https://github.com/riscv/riscof.git@d38859f ```

I did not test this yet (or checked the Verilog standard), but if there was no casting to `WIDTH` in the RHS, than the signal `ena` and the decimal constant...