Jakub Chlanda
Jakub Chlanda
> Aha! Am I understanding this right that the problem is due to the AMD target expecting all 3 dimensions in the "reqd_work_group_size" metadata node? If so, I can see...
> > > Regarding the naming, would this problem (and solution) not also apply to `work_group_size_hint` metadata? If so, could this metadata you're adding be made more general somehow? Maybe...
> What I am now considering is whether we should go back on that approach and instead always do the padding (not only for HIP/CUDA) as well as always add...
The [gen12](https://github.com/intel/llvm/actions/runs/9093375939/job/24992839378#step:22:2524) failures doesn't seem to be related to this PR.
@intel/llvm-gatekeepers this is ready to go now, thank you.
This was suggested a while back, here: https://github.com/intel/llvm/pull/6878#issuecomment-1483563291
@dm-vodopyanov @al42and would you like me to do anything else for this patch?
@intel/llvm-gatekeepers this should be ready to go. Thank you!
> > @intel/llvm-gatekeepers this should be ready to go. > > Thank you! > > @jchlanda, we need a review from @intel/unified-runtime-reviewers: > >  My bad sorry, was a...
@intel/llvm-gatekeepers we've got all the approvals now, should be ready to go. Thank you!