James Bowman

Yes, link is correct. Attached: [crdcsrvy.pdf](https://github.com/jamesbowman/sincos/files/861973/crdcsrvy.pdf)

(Looking at this because my verilog sincos is suddenly a timing critical path.) A straight 1-cycle implementation of 16-bit CORDIC must do 15 additions, inspecting the MSB of each addition....

The module is only computing `sin(x)`, in Verilog: ``` module isin( input signed [15:0] x, output signed [15:0] s); ``` so that is (polar -> rectangular) with r=1. So x0...

This diagram looks half-duplex, so the right sequence should be: spicl s w 0x40 r 2 u

This looks fine - the gaps on SCK are just the inter-byte pauses.  Hmm, one idea... datasheet does say that it expects a '1' bit before the 7-bit register...

Fixed the infinite loop bug, and pushed to PyPI: https://pypi.org/project/spidriver/ You can specify the size on the command-line using the ``-s`` argument, so for the MB85RS64V use ``-s 65536``, and...

That is puzzling. I expect there to be very little time between bytes. For ``read(10)`` there's be a delay every **10** bytes, because of the API overhead, but not every...

I'm just running the SPIDriver on the bench here and I see the same thing. The issue is that SPIDriver uses two-way communication to implement reads. (SPI **Writes** are fast,...

@Kabron287 was getting an error because of missing 'wx' - is it included in Python 3.7 on Windows? Or did you install wx by doing something like: https://wxpython.org/pages/downloads/index.html I have...

Python GUI should: - [ ] catch missing wx and show a helpful message - [ ] enumerate ports properly on Windows