when attempting to generate ingame circuit, nothing happens

[Catniped]

https://user-images.githubusercontent.com/80766200/223428201-4cd080b5-9ca5-461f-a9d4-8875a277d977.mp4

nothing found in logs, verilog used:

module or_not_halfadder (
  input Bit_1,
  input Bit_2,
  output Carry_out,
  output Sum
);
  assign Carry_out = ~ (~ Bit_1 | ~ Bit_2);
  assign Sum = ~ (~ (Bit_1 | Bit_2) | ~ (~ Bit_1 | ~ Bit_2));
endmodule

module or_not_fulladder (
  input A,
  input C,
  input B,
  output Carry,
  output Sum
);
  wire s0;
  wire s1;
  wire s2;
  or_not_halfadder or_not_halfadder_i0 (
    .Bit_1( A ),
    .Bit_2( B ),
    .Carry_out( s0 ),
    .Sum( s1 )
  );
  or_not_halfadder or_not_halfadder_i1 (
    .Bit_1( s1 ),
    .Bit_2( C ),
    .Carry_out( s2 ),
    .Sum( Sum )
  );
  assign Carry = (s0 | s2);
endmodule

module \4_bit_adder  (
  input bit1_1,
  input bit2_1,
  input bit3_1,
  input bit4_1,
  input bit1_2,
  input bit2_2,
  input bit3_2,
  input bit4_2,
  output bit2_out,
  output bit3_out,
  output bit4_out,
  output bit5_out,
  output bit1_out
);
  wire s0;
  wire s1;
  wire s2;
  or_not_halfadder or_not_halfadder_i0 (
    .Bit_1( bit1_1 ),
    .Bit_2( bit1_2 ),
    .Carry_out( s0 ),
    .Sum( bit1_out )
  );
  or_not_fulladder or_not_fulladder_i1 (
    .A( s0 ),
    .C( bit2_1 ),
    .B( bit2_2 ),
    .Carry( s1 ),
    .Sum( bit2_out )
  );
  or_not_fulladder or_not_fulladder_i2 (
    .A( s1 ),
    .C( bit3_1 ),
    .B( bit3_2 ),
    .Carry( s2 ),
    .Sum( bit3_out )
  );
  or_not_fulladder or_not_fulladder_i3 (
    .A( s2 ),
    .C( bit4_1 ),
    .B( bit4_2 ),
    .Carry( bit5_out ),
    .Sum( bit4_out )
  );
endmodule

[Catniped]

tried with this verilog, same result:

module and_or_xor (
  input bit1,
  input bit2,
  output bitO
);
  assign bitO = ~ (~ (bit1 | bit2) | ~ (~ bit1 | ~ bit2));
endmodule

[programmeruser2]

Pretty sure you have to add some sort of power source like a button to make it work as the gif in the README showed