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Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.
New guidelines should provide clear expectations from incoming pull requests and also give hints on how to write tests for particular types of changes.
Signed-off-by: Mariusz Merecki
sycl::double2 type degrades sycl performance on NV GPU with additional generated memory instructions
**Describe the bug** sycl::double2 type passed to a kernel function significantly degrades sycl performance on NV GPU with numerous, additional generated memory instructions compared to CUDA implementation baseline **Description** 1)...
To avoid mistakes with passing a copy of 'reducer' argument reducer's copy constructors were marked as delete. Issue: https://github.com/intel/llvm/issues/6065
This is to complement this [PR](https://github.com/intel/llvm/pull/6469) which removes \ headers to comply with LLVM Coding Standards. Signed-off-by: Rauf, Rana
**Describe the bug** When compiling a file for the HIP backend (`-fsycl-targets=amdgcn-amd-amdhsa`) it is necessary to specify `--offload-target`. However, when trying to compile for the CUDA backend in the same...
For in-order queues we can reuse events even before they are completed and released. Simplified scheme looks like this: submit command1 [] -> pi_event1 (ze_event1) submit command2 [dep pi_event1] ->...