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Add the "phase 2" design for if_device_has and if_architecture_is extensions. Whereas the phase 1 design worked only in some limited cases for AOT compilation, the phase 2 design fully supports both of these extensions in both AOT and JIT modes.

The phase 2 design is also implementable in a 1-pass compiler.

Note that the design document presents a primary design and also two alternatives. Discussion of the alternatives is encouraged in this PR.

Attention @intel/dpcpp-spirv-doc-reviewers: The SPIR-V extension specification in this PR is used only in one of the alternate designs. Although comments on the SPIR-V spec are welcome, it may make sense to decide first whether the alternate design makes sense before doing a detailed review of the SPIR-V spec.