dspatch

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Signal update timing and simulation of programmable logic

4

Hi, I'm looking into dspatch as a framework for emulating the behavior of programmable logic on an FPGA. dspatch looks perfect, except for a timing issue I cannot resolve. For...

AndreasAlbert

A diagram illustrating how different parts of dspatch are interconnected would be highly appreciated.

shujaatak

Error processing mechanism and automatically Type/Format negotiation

4

Do you have any plan for Error processing mechanism and automatically Type/Format negotiation between components?

vacing

named and optional IO

3

It is quite simple and refreshing indeed. It would be nice to add named inputs/outputs so that components can be connected by name. It would be less bug prone, especially...

trporn

MarcusTomlinson

Is it possible to add an exception handling method? For example, Node B depends on the output of A. When node A crashes or throws an exception, the circuit diagram...

libaineu2004

In addition to execution diagram, you can dump the graph to a DOT format and visualize it using a number of free [GraphViz](https://www.graphviz.org/) tools. https://dreampuf.github.io/GraphvizOnline/ // dump the circuit graph...

libaineu2004

[Plugin Load] How do we distinguish between debug and release libraries?

3

Hello, As the title says, the cause is that when I load the release lib using debug it crashes, and vice versa. Is there already a way to distinguish between...

zmoth

Hi! How to implement a delay line component with single thread and no autotick. We are simulate digital logic with explicitly call Tick() only on input values change. Is where...

denxxjkee