pequeno_riscv

Pequeno (meaning "tiny" in Spanish) aka PQR5 is a 5-staged pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Overview

• RV32I ISA v2.2 + custom instructions

  Assembler and Instruction Manual: https://github.com/iammituraj/pqr5asm)

  FPGA demo of Pequeno running Hello world program: https://youtu.be/GECyL9U5ZxI

• Single-core, Single-issue, In-order execution

• Classic 5-stage RISC-V pipeline

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                                    /     /  RISC-V 32I    /    /\
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    chipmunklogic.com                                                    [[[[[[[ O P E N - S O U R C E _
  

Important notes

Please through database_info.txt for information about the repo organization and how to setup the pqr5 build environment

Disclaimer

This CPU core is intended for educational purposes only. Users are encouraged to review the accompanying license document (LICENSE) for detailed terms and conditions.

Developer

Mitu Raj, Chipmunk Logic, [email protected]