hpm-hal

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See-also: #36 > The RNG interrupt functionality appears to be non-functional due to the following reasons: > > - Lack of a FIFO-ready signal (FUFMOD usage unclear) > - Absence...

andelf

Fix SPI async busy wait

1

See-also #33 only async write is fixed. To get END irq work: - ~~DMA Bust must 1 for SPI~~ - ~~DMA transize must be **actual_size + 1** for SPI~~ **UPDATE**...

andelf

SPI finish interrupt is not working under DMA mode // Batch Async SPI Transfers with Bulk Data Exhibit Unreliable Behavior

2

It seems that Future returns before the SPI transfer has finished. Only occurs when **bulk** data is transferred under **slow** SPI frequency. **UPDATE**: SPI finish interrupt is not working under...

andelf

The following crashes MCU: ```rust let x = 0xf40c01c0 as *const u32; // any invalid address let y = unsafe { *x }; defmt::info!("y = {}", y); ``` Note that...

andelf

To Reproduce: ```rust #![no_main] #![no_std] use embedded_hal::delay::DelayNs; use hal::gpio::{Level, Output, Speed}; use hal::pac; use riscv::delay::McycleDelay; use {defmt_rtt as _, hpm_hal as hal, riscv_rt as _}; #[hpm_hal::entry] #[link_section = ".fast"] fn...

andelf

Update to latest `embassy-time-driver`

HaoboGu