Warning: This code does not work properly

[AgnerF]

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The transmitter fails to set the stop bit high. The receiver is unstable because it does not sample in the middle of the clock interval.

[AgnerF]

Here is a useful alternative https://github.com/nandland/nandland/tree/master/UART

[ccattuto]

Check out this fork, too. It fixes those issues and was tested on an FPGA: https://github.com/ccattuto/verilog-uart

[Nado15]

I noticed that the transmitter does not set the the stop bit (out = 1'b1) https://github.com/hell03end/verilog-uart/blob/cad12f92f848973e8f63c95fe7a9af0601b8773b/uart/Uart8Transmitter.v#L56-L60

Also, I believe an error also occurs when the done signal is set to 1 for the first time. Busy and Done are both 1, but the code never sets busy and done to 1 in the same cycle. According to the image below, its this is the case, so I assume the image is wrong