hdl-modules
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A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Trail
Resync
In `resync_twophase.tcl` and `resync_twophase_handshake.tcl`. As discussed here: https://support.xilinx.com/s/question/0D74U000007uIz1SAE/detail?language=en_US
Seems that quartus is more strict in some senses. Would be cool if things could be used with quartus. Especially people with the pro license so that VHDL-2008 can be...
Inspired by this verilog code it is possible to check for fifo full without converting read pointer to binary. Could save some LUTs. ``` assign wfull_nxt = (wgray_nxt == {~wq2_rgray[AW:AW-1],...
"open source" and "permissible license" should be on every module page. Also on every readme in the repo. Also on the index page? Think about other terms that should be...
Bumps [actions/checkout](https://github.com/actions/checkout) from 5.0.0 to 6.0.0. Release notes Sourced from actions/checkout's releases. v6.0.0 What's Changed Update README to include Node.js 24 support details and requirements by @salmanmkc in actions/checkout#2248 Persist...
Bumps [awalsh128/cache-apt-pkgs-action](https://github.com/awalsh128/cache-apt-pkgs-action) from 1.5.3 to 1.6.0. Release notes Sourced from awalsh128/cache-apt-pkgs-action's releases. v1.6.0 What's Changed fix: skip invalid lines by @SMoraisAnsys in awalsh128/cache-apt-pkgs-action#160 Add if-empty-packages optional input by @tueda in...