Document STAT interrupt oddities

[ISSOtm]

<LIJI> Mode 2 works differently in terms of interrupts because it's only checked at a single, specific M-cycle <LIJI> Meaning, enabling Mode 2 interrupt during Mode 2 will not trigger an interrupt <LIJI> and similarly, mode 2 cannot block interrupts <LIJI> So enabling the LYC interrupt during mode 2 can trigger an interrupt even if Mode 2's interrupt is already enabled <ISSOtm> Also, wasn't LY=LYC immune to being blocked by Mode 0 due to some delay? <LIJI> I think there's something like that but I'd have to check SameBoy's source