ERROR: Invalid global constant node 'INT_L_X0Y112/VCC_WIRE'

[Demindiro]

Hello,

I'm trying generate a bitstream for the Arty A7-100T with the following design:

module shine (
	output led_r,
	output led_g,
	input switch_g
);

assign led_r = 1;
assign led_g = switch_g;

endmodule

set_property PACKAGE_PIN G6 [get_ports led_r]
set_property PACKAGE_PIN F6 [get_ports led_g]
set_property PACKAGE_PIN A8 [get_ports switch_g]
set_property IOSTANDARD LVCMOS33 [get_ports led_r]
set_property IOSTANDARD LVCMOS33 [get_ports led_g]
set_property IOSTANDARD LVCMOS33 [get_ports switch_g]

I run the following commands:

yosys shine.v -p "synth_xilinx -top shine; write_json shine.json"
nextpnr-xilinx --chipdb /usr/local/nextpnr/xilinx-chipdb/xc7a100t.bin --xdc arty.xdc --json shine.json --write aaa_routed.json --fasm aaa.fasm

Both are build from source (Yosys 0.24+1 (git sha1 7ad7b550c, gcc 10.2.1-6 -Os), nextpnr-xilinx -- Next Generation Place and Route (Version 51731e8a))

With xc7a35t.bin P&R appears to work (haven't tested it on real hardware as I don't have a 35T), but with xc7a100t.bin it gives the error Invalid global constant node 'INT_L_X0Y112/VCC_WIRE'.

The following issue in prjxray appears to be related: https://github.com/f4pga/prjxray/issues/440, so I'm not sure if it is actually an issue with nextpnr-xilinx. I'm going to try to generate the database myself and see if that works.