embarc_osp
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arc_startup.s : SR to AUX_DC_IVDC should wait on FS bit
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Issue Summary
- Type: Bug
- Category: Library
- Priority: Medium
- Release Version: All
Bug
Development Environment
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HOST OS All
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TOOLCHAIN All
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BOARD N/A
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ARC CORE All
Bug Description
arc_startup.s line 81-82, here data cache is invalidated by writing to AUX_DC_IVDC and it is immediately enabled by writing to AUX_DC_CTRL. But according to documentation you first should wait on FS bit in DC_CTRL.