incosistency in cyclecount results

[benhaim1]

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Issue Summary

• Type: Bug | Enhancement | Question
• Category: ARC HAL | Device HAL | BSP | OS | Middleware | Library | Example | Build System | Tools | Documentation | Installation | Usability
• Priority: Urgent | High | Medium | Low
• Release Version: Specified version such as 2016.05 or All

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Bug

Development Environment

FreeRTOS

• TOOLCHAIN MWDT L-2019.03

• BOARD nSIM

• ARC CORE default

Bug Description

Hi,

I obtained inconsistent results in different runs of the kernel example. Appreciate your help

Please see below:

C:\Users\benhaim\Downloads\embarc_osp-master\example\freertos\kernel>gmake BOARD=nsim -j4 gui "Download & Debug obj_nsim_10/mw_arcem/freertos_kernel_mw_arcem.elf" mdb -nooptions -nogoifmain -toggle=include_local_symbols=1 -OS=FreeRTOS -nsim -off=binary_stdin -off=binary_stdout -on=load_at_paddr -on=reset_upon_restart -off=flush_pipe -off=cr_for_more -OKN -prop=nsim_isa_host_timer=1 -prop=nsim_isa_host_timer_mhz=10 @obj_nsim_10/mw_arcem/embARC_generated/mdb.arg obj_nsim_10/mw_arcem/freertos_kernel_mw_arcem.elf Using Oracle Corporation Java version 1.8.0_152 on Windows. Welcome to the GUI version of the MetaWare Debugger, vP-2019.03 (build 008) (1561). SmaRT Build Configuration Register: 0x2003 (stack size=8) ELF segment #0 paddr 0x000000 size 0x0087a8 ..... ELF segment #1 paddr 0x008800 size 0x0009dc vaddr 0x80000000 .Error in evaluating expression `&xQueueRegistry'.

License SeeCode expires in 227 days.

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| _ \ _____ _____ _ __ ___ | | __ ) _ _ | |_) / _ \ \ /\ / / _ \ '/ _ / | _ \| | | | | __/ (_) \ V V / __/ | | __/ (_| | |_) | |_| | |_| \___/ \_/\_/ \___|_| \___|\__,_|____/ \__, | |___/ _ _ ____ ____ ___ _ __ ___ | |__ / \ | _ \ / ___| / _ \ '_ _ | ' \ / _ \ | |) | | | __/ | | | | | |) / ___ | _ <| |___ _|| || ||.// __| _\___|

embARC Build Time: Jun 18 2019, 18:25:17 Compiler Version: Metaware, 4.2.1 Compatible Clang 6.0.1 (branches/release_60) Benchmark CPU Frequency: 1000000 Hz Benchmark will run 200 times, please wait about 400 ms

Average benchmark result list as follows: extra measurement cost : 21474835 cycles task2 -> task1 : 449 cycles task1 -> int : 199 cycles int -> nest int : 249 cycles nest int -> int : 49 cycles int -> task1 : 21474835 cycles task1 -> task2 : 399 cycles mux: tsk1 -> tsk2 : 749 cycles sem: tsk1 -> tsk2 : 1099 cycles evt: tsk1 -> tsk2 : 499 cycles dtq: tsk1 -> tsk2 : 849 cycles

freeRTOS:There are now 4 tasks. Shutting down all processes...Done

C:\Users\benhaim\Downloads\embarc_osp-master\example\freertos\kernel>gmake BOARD=nsim -j4 run "Download & Run obj_nsim_10/mw_arcem/freertos_kernel_mw_arcem.elf" mdb -nooptions -nogoifmain -toggle=include_local_symbols=1 -OS=FreeRTOS -nsim -off=binary_stdin -off=binary_stdout -on=load_at_paddr -on=reset_upon_restart -off=flush_pipe -off=cr_for_more -OKN -prop=nsim_isa_host_timer=1 -prop=nsim_isa_host_timer_mhz=10 @obj_nsim_10/mw_arcem/embARC_generated/mdb.arg -run obj_nsim_10/mw_arcem/freertos_kernel_mw_arcem.elf SmaRT Build Configuration Register: 0x2003 (stack size=8) Initializing. System name is ARC_DLL; my DLL was C:/ARC/MetaWare/arc/bin/freertos. freeRTOS: there are 4 task priorities. Error in evaluating expression `&xQueueRegistry'. Current task is 0: denotes current task in _arc_reset.

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| _ \ _____ _____ _ __ ___ | | __ ) _ _ | |_) / _ \ \ /\ / / _ \ '/ _ / | _ \| | | | | __/ (_) \ V V / __/ | | __/ (_| | |_) | |_| | |_| \___/ \_/\_/ \___|_| \___|\__,_|____/ \__, | |___/ _ _ ____ ____ ___ _ __ ___ | |__ / \ | _ \ / ___| / _ \ '_ _ | ' \ / _ \ | |) | | | __/ | | | | | |) / ___ | _ <| |___ _|| || ||.// __| _\___|

embARC Build Time: Jun 18 2019, 18:25:17 Compiler Version: Metaware, 4.2.1 Compatible Clang 6.0.1 (branches/release_60) Benchmark CPU Frequency: 1000000 Hz Benchmark will run 200 times, please wait about 400 ms

Average benchmark result list as follows: extra measurement cost : 21474835 cycles task2 -> task1 : 21474835 cycles task1 -> int : 21474835 cycles int -> nest int : 21474835 cycles nest int -> int : 21474835 cycles int -> task1 : 21474835 cycles task1 -> task2 : 21474835 cycles mux: tsk1 -> tsk2 : 21474835 cycles sem: tsk1 -> tsk2 : 21474835 cycles evt: tsk1 -> tsk2 : 21474835 cycles dtq: tsk1 -> tsk2 : 21474835 cycles

The data cache control register is not set to flush locked lines. The debugger's memory reads may be inconsistent with data in the data cache. This warning will not repeat.freeRTOS:There are now 4 tasks. Current task has switched to ( 2) 0x80004e98: task2 (current) in _exit_loop -- prio 3 rdy run 0 (0%).