esp-hal
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esp-rs
Cache/Memory mapping
Copied from https://github.com/esp-rs/esp-hal/issues/954#issuecomment-1816696280
Huh, last time I went looking into how the cache works it was all ROM code and zero docs. Now there is a esp_mm component: https://github.com/espressif/esp-idf/tree/c8243465e45489835d645bf217a6929fd0c01b7f/components/esp_mm with some docs as to how it works. Maybe we should try and port some of this into esp-hal.
We could replace this piece of code (which is currently hardcoded) with a proper cache driver.
One limitation we have is that I don't think any of the cache registers are in the SVDs - but it looks like there is only one register with just a few bits: https://github.com/espressif/esp-idf/blob/c8243465e45489835d645bf217a6929fd0c01b7f/components/esp_mm/include/esp_cache.h#L21-L47
Ah we actually configure something for S3, didn't knew that 🤔 Oh - that was me
Ah we actually configure something for S3, didn't knew that 🤔 Oh - that was me
Is the DCACHE only enabled when using the PSRAM driver?
I think for most targets the second stage bootloader will enable it and use whatever was configured when building it For S3 (something I re-learned) we always configure it in esp-hal. It's a bit inconsistent IMHO