David Chisnall

> Strong disagree. An app-specific clipboard flies in the face of the purpose of copy and paste, i.e. inter-app communication. Let's not reinvent the PRIMARY and CLIPBOARD and similar X11...

> However, I am also using it for my PRs but constantly enabling and disabling auto-formatting for existing code is quite tedious. There's a clang-format-diff.py script included with clang-format that...

> In an ideal world if a line is too long the coding standard is that the method call is broken up with the colons at the end of each...

This feels like overfitting for particular pipeline shapes. Large pipeline can always use the same rename registers for 128-bit SIMD registers and capability registers. Simple implementations will find things like...

> LC/SC with tag stripping is extremely close to what we need. Defining LC / SC as tag clearing if not aligned would, I think, mostly be fine, but emphasis...

> It's _how_ we enable the registers to be reused as 128-bit SIMD registers that I'm particularly trying to address. No, it's how to enable *architectural* registers to be reused...

This sounds completely impossible for a compiler to use. Knowledge of what memory region an object is in, and therefore whether it can be tagged, is not tracked. You could...

> a CHERI version would be faster than non-CHERI I don't see how that would be the case. The implementation of these is usually independent of the register size. There...

> Mismatching stores "fizzle" rather than trap: the store instruction may commit prior to knowing the memory metadata tag value, and mismatch results in the store being silently dropped without...

To give a bit of history: The early versions of CHERI MIPS did not have immediate offsets for the loads and stores. Most of the time, this was purely a...