Carlos Eduardo

Bloop also does not install on arm64 Linux hosts using AdoptOpenJDK 8: ``` ❯ cs install --jvm 8 bloop https://repo1.maven.org/maven2/io/get-coursier/apps/maven-metadata.xml No new update since 2021-03-02 07:43:10 https://repo1.maven.org/maven2/ch/epfl/scala/bloopgun_2.12/maven-metadata.xml No new update...

Just adding that I haven't used Homebrew to install Coursier on Linux. Used the native binary directly and then `cs install cs`.

Ping... any news about this? Might be related to https://symbiflow.slack.com/archives/CGCL3DBMM/p1639411001290300 Slack

Awesome, I'm about to get a Kintex7 FPGA (from Ali as well ;) ) and might get the Segger too :) Let me know once it arrives!

That's awesome. I've recently ordered one so it's not here yet. I'll report back once I test it out. Thanks a lot for the quickness of implementing it! :D

@trabucayre sorry about the absurdely delayed answer. I've moved houses in the past months and some of my stuff got packed away (including the segger cable by accident).

Maybe start a "Cookbook" like doc aggregating the most used scenarios using chiseltest is a good idea.

I have already started a draft implementation of this feature but the main problem where I'm stuck is how to place these directives inline with the declaration before the object's...

I plan on looking into this again, I wonder what's the best approach and syntax to use this, Verilog-1995 or Verilog-2001. As an example here: https://www.intel.com/content/www/us/en/support/programmable/articles/000074381.html: Verilog-1995: `output reg my_reg...

I'll test this out but believe the readmem should be generated for all memories since they could contain different content and initialization right?