Carlos Eduardo comments

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                                            Carlos Eduardo

Create scala-extensions module for Scala 3

Cool, thanks for the merge Johan! I'll look into the examples if then might get an update but I believe the tests are pretty self-explanatory.

cs java --installed takes 11 seconds to finish

Recently, the time to list all installed JVMs have gone up (I believe because the size of the index grew). I takes almost 1 minute in my 16'' Intel MBP:...

Chisel design with inline blackbox verilog generates `.sv` output with filenames at the end

I believe even having the split files option, this is still a bug since the two resource files were correctly inlined in the generated SV file but the filenames were...

Chisel design with inline blackbox verilog generates `.sv` output with filenames at the end

Bump. Any feedback if this is supposed to be a bug and the filelist output could be suppressed from the output SV? I could look into providing a PR with...

Chisel design with inline blackbox verilog generates `.sv` output with filenames at the end

Closing thoughts here... so I understand the '-o' option to output a single-file .sv plans to be deprecated and the way to go is keep generating split files for each...

[FIRRTL] Feature Request: Provide a similar `--target:fpga` behavior for FPGA-suited targets

I've been collecting some options that makes FPGA synthesis work fine as in: ```scala ChiselStage.emitSystemVerilogFile( new Toplevel(board, invreset, cpufreq), chiselArgs.value.toArray, Array( "--strip-debug-info", // Disables reg and memory randomization on initialization...

[FIRRTL] Feature Request: Provide a similar `--target:fpga` behavior for FPGA-suited targets

Also to have memory initialization on synthesis tool, passing a define in the synthesis is required (like `-DENABLE_INITIAL_MEM_` in verilator or `-Dname=ENABLE_INITIAL_MEM_` in Yosys. Ref. https://github.com/llvm/circt/issues/4752#issuecomment-1696021770

Add Scala executable via GraalVM. Bump versions.

News on this?

Bump org.scala-lang:scala3-interfaces from 3.3.1 to 3.4.1

Better bump to 3.3.3 instead of 3.4.1 to keep on LTS versions.

Memory leak when vCenter is down (host is unreachable)

To give a broad overview, here is the behaviour of the exporter during use and then with vCenter down: ![image](https://user-images.githubusercontent.com/20382/93894135-c3622480-fcc4-11ea-89ed-d7c1dfcde3c7.png) Until 21:30, vCenter was up... memory use was steady... from...