Carlos Eduardo

Ah yes, you mean the problem pointed-out by https://github.com/chipsalliance/chisel3/issues/1289 right?

Ping... news about this?

Same here while trying to make a RAM module: ```scala class SinglePortRAM(sizeKB: Int = 1, width: Int = 32, memoryFile: String = "") extends Module { val addrWidth = chiselTypeOf((sizeKB...

Hey Kevin, thanks for your response. I understand I cannot pass the .hex file I have to be loaded at synthesis by using the annotation, right since it only supports...

As someone new to HDLs, I found these methods way more complex than just `$readmemh(mem, "file")` in Verilog... I believe that it should have a somewhat similar syntax...

Thanks @ekiwi ... just a heads-up is that since the memory gets initialized by directly setting the memory array in Verilog so a 1k Scala module with an 11k .hex...

It's instantiated into a 16KB ram that would be pretty much empty.. but still quite a grow. I still need to test it thru all synthesis... i'll let u know...

@antonblanchard check out https://github.com/chipsalliance/firrtl/pull/2107. I've added a new annotation allowing inline readmem in Verilog emiter. Your sample code would become: ```scala import chisel3._ import chisel3.experimental.{ChiselAnnotation, annotate} import firrtl.annotations.{MemoryFileInlineAnnotation} class Foo(val...

Now there is also a method in chisel for this: ```scala import chisel3.util.experimental.loadMemoryFromFileInline ... annotate(new ChiselAnnotation { override def toFirrtl = MemorySynthInit }) val mem = SyncReadMem(1024, UInt(width.W)) loadMemoryFromFileInline(mem, memoryFile)...

Ah yes, that would be great!