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SAMD21G18A TCC3 Timer Support
I've been trying to use TCC3 on the SAMD21 in a project, but there is not support for it in Arduino. It looks like Atmel/Microchip added TCC3 in a later silicon revision. Is there any way I could get these built?
I'm willing to do it myself, but I'm afraid I don't have the know-how.
You find everything you need in the datasheet, I just started by creating tcc3.h from tcc0.h (as it has the same specs) for my own hackaround:
/**
* \file
*
* \brief Instance description for TCC3
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_TCC3_INSTANCE_
#define _SAMD21_TCC3_INSTANCE_
/* ========== Register definition for TCC3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC3_CTRLA (0x42006000U) /**< \brief (TCC3) Control A */
#define REG_TCC3_CTRLBCLR (0x42006004U) /**< \brief (TCC3) Control B Clear */
#define REG_TCC3_CTRLBSET (0x42006005U) /**< \brief (TCC3) Control B Set */
#define REG_TCC3_SYNCBUSY (0x42006008U) /**< \brief (TCC3) Synchronization Busy */
#define REG_TCC3_FCTRLA (0x4200600CU) /**< \brief (TCC3) Recoverable Fault A Configuration */
#define REG_TCC3_FCTRLB (0x42006010U) /**< \brief (TCC3) Recoverable Fault B Configuration */
#define REG_TCC3_WEXCTRL (0x42006014U) /**< \brief (TCC3) Waveform Extension Configuration */
#define REG_TCC3_DRVCTRL (0x42006018U) /**< \brief (TCC3) Driver Control */
#define REG_TCC3_DBGCTRL (0x4200601EU) /**< \brief (TCC3) Debug Control */
#define REG_TCC3_EVCTRL (0x42006020U) /**< \brief (TCC3) Event Control */
#define REG_TCC3_INTENCLR (0x42006024U) /**< \brief (TCC3) Interrupt Enable Clear */
#define REG_TCC3_INTENSET (0x42006028U) /**< \brief (TCC3) Interrupt Enable Set */
#define REG_TCC3_INTFLAG (0x4200602CU) /**< \brief (TCC3) Interrupt Flag Status and Clear */
#define REG_TCC3_STATUS (0x42006030U) /**< \brief (TCC3) Status */
#define REG_TCC3_COUNT (0x42006034U) /**< \brief (TCC3) Count */
#define REG_TCC3_PATT (0x42006038U) /**< \brief (TCC3) Pattern */
#define REG_TCC3_WAVE (0x4200603CU) /**< \brief (TCC3) Waveform Control */
#define REG_TCC3_PER (0x42006040U) /**< \brief (TCC3) Period */
#define REG_TCC3_CC0 (0x42006044U) /**< \brief (TCC3) Compare and Capture 0 */
#define REG_TCC3_CC1 (0x42006048U) /**< \brief (TCC3) Compare and Capture 1 */
#define REG_TCC3_CC2 (0x4200604CU) /**< \brief (TCC3) Compare and Capture 2 */
#define REG_TCC3_CC3 (0x42006050U) /**< \brief (TCC3) Compare and Capture 3 */
#define REG_TCC3_PATTB (0x42006064U) /**< \brief (TCC3) Pattern Buffer */
#define REG_TCC3_WAVEB (0x42006068U) /**< \brief (TCC3) Waveform Control Buffer */
#define REG_TCC3_PERB (0x4200606CU) /**< \brief (TCC3) Period Buffer */
#define REG_TCC3_CCB0 (0x42006070U) /**< \brief (TCC3) Compare and Capture Buffer 0 */
#define REG_TCC3_CCB1 (0x42006074U) /**< \brief (TCC3) Compare and Capture Buffer 1 */
#define REG_TCC3_CCB2 (0x42006078U) /**< \brief (TCC3) Compare and Capture Buffer 2 */
#define REG_TCC3_CCB3 (0x4200607CU) /**< \brief (TCC3) Compare and Capture Buffer 3 */
#else
#define REG_TCC3_CTRLA (*(RwReg *)0x42006000U) /**< \brief (TCC3) Control A */
#define REG_TCC3_CTRLBCLR (*(RwReg8 *)0x42006004U) /**< \brief (TCC3) Control B Clear */
#define REG_TCC3_CTRLBSET (*(RwReg8 *)0x42006005U) /**< \brief (TCC3) Control B Set */
#define REG_TCC3_SYNCBUSY (*(RoReg *)0x42006008U) /**< \brief (TCC3) Synchronization Busy */
#define REG_TCC3_FCTRLA (*(RwReg *)0x4200600CU) /**< \brief (TCC3) Recoverable Fault A Configuration */
#define REG_TCC3_FCTRLB (*(RwReg *)0x42006010U) /**< \brief (TCC3) Recoverable Fault B Configuration */
#define REG_TCC3_WEXCTRL (*(RwReg *)0x42006014U) /**< \brief (TCC3) Waveform Extension Configuration */
#define REG_TCC3_DRVCTRL (*(RwReg *)0x42006018U) /**< \brief (TCC3) Driver Control */
#define REG_TCC3_DBGCTRL (*(RwReg8 *)0x4200601EU) /**< \brief (TCC3) Debug Control */
#define REG_TCC3_EVCTRL (*(RwReg *)0x42006020U) /**< \brief (TCC3) Event Control */
#define REG_TCC3_INTENCLR (*(RwReg *)0x42006024U) /**< \brief (TCC3) Interrupt Enable Clear */
#define REG_TCC3_INTENSET (*(RwReg *)0x42006028U) /**< \brief (TCC3) Interrupt Enable Set */
#define REG_TCC3_INTFLAG (*(RwReg *)0x4200602CU) /**< \brief (TCC3) Interrupt Flag Status and Clear */
#define REG_TCC3_STATUS (*(RwReg *)0x42006030U) /**< \brief (TCC3) Status */
#define REG_TCC3_COUNT (*(RwReg *)0x42006034U) /**< \brief (TCC3) Count */
#define REG_TCC3_PATT (*(RwReg16*)0x42006038U) /**< \brief (TCC3) Pattern */
#define REG_TCC3_WAVE (*(RwReg *)0x4200603CU) /**< \brief (TCC3) Waveform Control */
#define REG_TCC3_PER (*(RwReg *)0x42006040U) /**< \brief (TCC3) Period */
#define REG_TCC3_CC0 (*(RwReg *)0x42006044U) /**< \brief (TCC3) Compare and Capture 0 */
#define REG_TCC3_CC1 (*(RwReg *)0x42006048U) /**< \brief (TCC3) Compare and Capture 1 */
#define REG_TCC3_CC2 (*(RwReg *)0x4200604CU) /**< \brief (TCC3) Compare and Capture 2 */
#define REG_TCC3_CC3 (*(RwReg *)0x42006050U) /**< \brief (TCC3) Compare and Capture 3 */
#define REG_TCC3_PATTB (*(RwReg16*)0x42006064U) /**< \brief (TCC3) Pattern Buffer */
#define REG_TCC3_WAVEB (*(RwReg *)0x42006068U) /**< \brief (TCC3) Waveform Control Buffer */
#define REG_TCC3_PERB (*(RwReg *)0x4200606CU) /**< \brief (TCC3) Period Buffer */
#define REG_TCC3_CCB0 (*(RwReg *)0x42006070U) /**< \brief (TCC3) Compare and Capture Buffer 0 */
#define REG_TCC3_CCB1 (*(RwReg *)0x42006074U) /**< \brief (TCC3) Compare and Capture Buffer 1 */
#define REG_TCC3_CCB2 (*(RwReg *)0x42006078U) /**< \brief (TCC3) Compare and Capture Buffer 2 */
#define REG_TCC3_CCB3 (*(RwReg *)0x4200607CU) /**< \brief (TCC3) Compare and Capture Buffer 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TCC3 peripheral ========== */
#define TCC3_CC_NUM 4 // Number of Compare/Capture units
#define TCC3_DITHERING 1 // Dithering feature implemented
#define TCC3_DMAC_ID_MC_0 0x2E
#define TCC3_DMAC_ID_MC_1 0x2F
#define TCC3_DMAC_ID_MC_2 0x30
#define TCC3_DMAC_ID_MC_3 0x31
#define TCC3_DMAC_ID_MC_LSB 0x2E
#define TCC3_DMAC_ID_MC_MSB 0x31
#define TCC3_DMAC_ID_MC_SIZE 4
#define TCC3_DMAC_ID_OVF 0x2D // DMA overflow/underflow/retrigger trigger
#define TCC3_DTI 1 // Dead-Time-Insertion feature implemented
#define TCC3_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
#define TCC3_GCLK_ID 37 // Index of Generic Clock
#define TCC3_OTMX 1 // Output Matrix feature implemented
#define TCC3_OW_NUM 8 // Number of Output Waveforms
#define TCC3_PG 1 // Pattern Generation feature implemented
#define TCC3_SIZE 24
#define TCC3_SWAP 1 // DTI outputs swap feature implemented
#define TCC3_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
#endif /* _SAMD21_TCC3_INSTANCE_ */
Next, I added the following line 311 in samd21g18a.h (as I'm using this particular processor):
#include "instance/tcc3.h"
and line 411
#define TCC3 (0x42006000UL) /**< \brief (TCC3) APB Base Address */
and finally line 515:
#define TCC3 ((Tcc *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
Edit: If I make some mistakes on the way, feel free to tell me before I find out later.
Additionally, I added line 120:
TCC3_IRQn = 29, /**< 29 SAMD21G18A Timer Counter Control 3 (TCC3) */
and line 214:
void TCC3_Handler ( void );
Not to forget line 185 (after the reserved position 28):
void* pfnTCC3_Handler; /* 29 Timer Counter Control 3 */
and changing lines 519 and 520:
#define TCC_INST_NUM 4 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
Edit: Found one more position to change, lines 364-366:
#define ID_TCC3 85 /**< \brief Timer Counter Control 3 (TCC3) */
#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */
So this is now my total samd21g18.h:
/**
* \file
*
* \brief Header file for SAMD21G18A
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21G18A_
#define _SAMD21G18A_
/**
* \ingroup SAMD21_definitions
* \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
* This file defines all structures and symbols for SAMD21G18A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#define CAST(type, value) ((type *)(value))
#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
#else
#define CAST(type, value) (value)
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
#endif
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMD21G18A */
/* ************************************************************************** */
/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
TCC3_IRQn = 29, /**< 29 SAMD21G18A Timer Counter Control 3 (TCC3) */
TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
void* pfnTCC3_Handler; /* 29 Timer Counter Control 3 */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NMI_Handler ( void );
void HardFault_Handler ( void );
void SVC_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void PM_Handler ( void );
void SYSCTRL_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void USB_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TCC3_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void TC5_Handler ( void );
void ADC_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void PTC_Handler ( void );
void I2S_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samd21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
/* ************************************************************************** */
/** \defgroup SAMD21G18A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/dac.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/i2s.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rtc.h"
#include "component/sercom.h"
#include "component/sysctrl.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/usb.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
/* ************************************************************************** */
/** \defgroup SAMD21G18A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc.h"
#include "instance/dac.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/gclk.h"
#include "instance/sbmatrix.h"
#include "instance/i2s.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/pac0.h"
#include "instance/pac1.h"
#include "instance/pac2.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/rtc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/sercom4.h"
#include "instance/sercom5.h"
#include "instance/sysctrl.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tc5.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tcc3.h"
#include "instance/usb.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
/* ************************************************************************** */
/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
// Peripheral instances on HPB1 bridge
#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_PORT 35 /**< \brief Port Module (PORT) */
#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
// Peripheral instances on HPB2 bridge
#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
#define ID_AC 81 /**< \brief Analog Comparators (AC) */
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
#define ID_TCC3 85 /**< \brief Timer Counter Control 3 (TCC3) */
#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
/* ************************************************************************** */
/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
#define TCC3 (0x42006000UL) /**< \brief (TCC3) APB Base Address */
#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PTC_GCLK_ID 34
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
#define TCC3 ((Tcc *)0x42006000UL) /**< \brief (TCC3) APB Base Address */
#define TCC_INST_NUM 4 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3 } /**< \brief (TCC) Instances List */
#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
#define USB_INSTS { USB } /**< \brief (USB) Instances List */
#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMD21G18A */
/* ************************************************************************** */
/** \defgroup SAMD21G18A_port PORT Definitions */
/*@{*/
#include "pio/samd21g18a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
/* ************************************************************************** */
#define FLASH_SIZE 0x40000UL /* 256 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 4096
#define FLASH_USER_PAGE_SIZE 64
#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
#define DSU_DID_RESETVALUE 0x10010005UL
#define EIC_EXTINT_NUM 16
#define PORT_GROUPS 2
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMD21G18A_H */
Next, I added in file evsys.h (instance) line 165:
#define EVSYS_ID_GEN_AC_COMP_2 74
#define EVSYS_ID_GEN_AC_COMP_3 75
#define EVSYS_ID_GEN_AC_WIN_1 76
#define EVSYS_ID_GEN_TCC3_OVF 77
#define EVSYS_ID_GEN_TCC3_TRG 78
#define EVSYS_ID_GEN_TCC3_CNT 79
#define EVSYS_ID_GEN_TCC3_MCX_0 80
#define EVSYS_ID_GEN_TCC3_MCX_1 81
#define EVSYS_ID_GEN_TCC3_MCX_2 82
#define EVSYS_ID_GEN_TCC3_MCX_3 83
and in line 206:
#define EVSYS_ID_USER_AC_SOC_2 29
#define EVSYS_ID_USER_AC_SOC_3 30
#define EVSYS_ID_USER_TCC3_EV_0 31
#define EVSYS_ID_USER_TCC3_EV_1 32
#define EVSYS_ID_USER_TCC3_MC_0 33
#define EVSYS_ID_USER_TCC3_MC_1 34
#define EVSYS_ID_USER_TCC3_MC_2 35
#define EVSYS_ID_USER_TCC3_MC_3 36
Next file to change was samd21g18a (pio) by adding the following lines:
/* ========== PORT definition for TCC3 peripheral ========== */
#DEFINE PIN_PA02F_TCC3_WO0 2L /**< \brief TCC3 signal: WO0 on PA02 mux F */
#DEFINE MUX_PA02F_TCC3_WO0 5L
#DEFINE PINMUX_PA02F_TCC3_WO0 ((PIN_PA02F_TCC3_WO0 << 16) | MUX_PA02F_TCC3_WO0)
#DEFINE PORT_PA02F_TCC3_WO0 (1ul << 2)
#DEFINE PIN_PA03F_TCC3_WO1 3L /**< \brief TCC3 signal: WO1 on PA03 mux F */
#DEFINE MUX_PA03F_TCC3_WO1 5L
#DEFINE PINMUX_PA03F_TCC3_WO1 ((PIN_PA03F_TCC3_WO1 << 16) | MUX_PA03F_TCC3_WO1)
#DEFINE PORT_PA03F_TCC3_WO1 (1ul << 3)
#DEFINE PIN_PB08F_TCC3_WO6 8L /**< \brief TCC3 signal: WO6 on PB08 mux F */
#DEFINE MUX_PB08F_TCC3_WO6 5L
#DEFINE PINMUX_PB08F_TCC3_WO6 ((PIN_PB08F_TCC3_WO6 << 16) | MUX_PB08F_TCC3_WO6)
#DEFINE PORT_PB08F_TCC3_WO6 (1ul << 8)
#DEFINE PIN_PB09F_TCC3_WO7 9L /**< \brief TCC3 signal: WO7 on PB09 mux F */
#DEFINE MUX_PB09F_TCC3_WO7 5L
#DEFINE PINMUX_PB09F_TCC3_WO7 ((PIN_PB09F_TCC3_WO7 << 16) | MUX_PB09F_TCC3_WO7)
#DEFINE PORT_PB09F_TCC3_WO7 (1ul << 9)
#DEFINE PIN_PA04F_TCC3_WO2 4L /**< \brief TCC3 signal: WO2 on PA04 mux F */
#DEFINE MUX_PA04F_TCC3_WO2 5L
#DEFINE PINMUX_PA04F_TCC3_WO2 ((PIN_PA04F_TCC3_WO2 << 16) | MUX_PA04F_TCC3_WO2)
#DEFINE PORT_PA04F_TCC3_WO2 (1ul << 4)
#DEFINE PIN_PA05F_TCC3_WO3 5L /**< \brief TCC3 signal: WO3 on PA05 mux F */
#DEFINE MUX_PA05F_TCC3_WO3 5L
#DEFINE PINMUX_PA05F_TCC3_WO3 ((PIN_PA05F_TCC3_WO3 << 16) | MUX_PA05F_TCC3_WO3)
#DEFINE PORT_PA05F_TCC3_WO3 (1ul << 5)
#DEFINE PIN_PA06F_TCC3_WO4 6L /**< \brief TCC3 signal: WO4 on PA06 mux F */
#DEFINE MUX_PA06F_TCC3_WO4 5L
#DEFINE PINMUX_PA06F_TCC3_WO4 ((PIN_PA06F_TCC3_WO4 << 16) | MUX_PA06F_TCC3_WO4)
#DEFINE PORT_PA06F_TCC3_WO4 (1ul << 6)
#DEFINE PIN_PA07F_TCC3_WO5 7L /**< \brief TCC3 signal: WO5 on PA07 mux F */
#DEFINE MUX_PA07F_TCC3_WO5 5L
#DEFINE PINMUX_PA07F_TCC3_WO5 ((PIN_PA07F_TCC3_WO5 << 16) | MUX_PA07F_TCC3_WO5)
#DEFINE PORT_PA07F_TCC3_WO5 (1ul << 7)
#DEFINE PIN_PB22F_TCC3_WO0 22L /**< \brief TCC3 signal: WO0 on PB22 mux F */
#DEFINE MUX_PB22F_TCC3_WO0 5L
#DEFINE PINMUX_PB22F_TCC3_WO0 ((PIN_PB22F_TCC3_WO0 << 16) | MUX_PB22F_TCC3_WO0)
#DEFINE PORT_PB22F_TCC3_WO0 (1ul << 22)
#DEFINE PIN_PB23F_TCC3_WO1 23L /**< \brief TCC3 signal: WO1 on PB23 mux F */
#DEFINE MUX_PB23F_TCC3_WO1 5L
#DEFINE PINMUX_PB23F_TCC3_WO1 ((PIN_PB23F_TCC3_WO1 << 16) | MUX_PB23F_TCC3_WO1)
#DEFINE PORT_PB23F_TCC3_WO1 (1ul << 23)
#DEFINE PIN_PA27F_TCC3_WO6 27L /**< \brief TCC3 signal: WO6 on PA27 mux F */
#DEFINE MUX_PA27F_TCC3_WO6 5L
#DEFINE PINMUX_PA27F_TCC3_WO6 ((PIN_PA27F_TCC3_WO6 << 16) | MUX_PA27F_TCC3_WO6)
#DEFINE PORT_PA27F_TCC3_WO6 (1ul << 27)
#DEFINE PIN_PA28F_TCC3_WO7 28L /**< \brief TCC3 signal: WO7 on PA28 mux F */
#DEFINE MUX_PA28F_TCC3_WO7 5L
#DEFINE PINMUX_PA28F_TCC3_WO7 ((PIN_PA28F_TCC3_WO7 << 16) | MUX_PA28F_TCC3_WO7)
#DEFINE PORT_PA28F_TCC3_WO7 (1ul << 28)
#DEFINE PIN_PA30F_TCC3_WO4 30L /**< \brief TCC3 signal: WO4 on PA30 mux F */
#DEFINE MUX_PA30F_TCC3_WO4 5L
#DEFINE PINMUX_PA30F_TCC3_WO4 ((PIN_PA30F_TCC3_WO4 << 16) | MUX_PA30F_TCC3_WO4)
#DEFINE PORT_PA30F_TCC3_WO4 (1ul << 30)
#DEFINE PIN_PA31F_TCC3_WO5 31L /**< \brief TCC3 signal: WO5 on PA31 mux F */
#DEFINE MUX_PA31F_TCC3_WO5 5L
#DEFINE PINMUX_PA31F_TCC3_WO5 ((PIN_PA31F_TCC3_WO5 << 16) | MUX_PA31F_TCC3_WO5)
#DEFINE PORT_PA31F_TCC3_WO5 (1ul << 31)
#DEFINE PIN_PB02F_TCC3_WO2 2L /**< \brief TCC3 signal: WO2 on PB02 mux F */
#DEFINE MUX_PB02F_TCC3_WO2 5L
#DEFINE PINMUX_PB02F_TCC3_WO2 ((PIN_PB02F_TCC3_WO2 << 16) | MUX_PB02F_TCC3_WO2)
#DEFINE PORT_PB02F_TCC3_WO2 (1ul << 2)
#DEFINE PIN_PB03F_TCC3_WO3 3L /**< \brief TCC3 signal: WO3 on PB03 mux F */
#DEFINE MUX_PB03F_TCC3_WO3 5L
#DEFINE PINMUX_PB03F_TCC3_WO3 ((PIN_PB03F_TCC3_WO3 << 16) | MUX_PB03F_TCC3_WO3)
#DEFINE PORT_PB03F_TCC3_WO3 (1ul << 3)
In the Power Manager (pm.h, component) I changed line 366:
uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
uint32_t :2; /*!< bit: 22..23 Reserved */
uint32_t TCC3_:1; /*!< bit: 24 TCC3 APB Clock Enable */
uint32_t :7; /*!< bit: 25..31 Reserved */
and added in line 420:
#define PM_APBCMASK_AC1_Pos 21 /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
#define PM_APBCMASK_AC1 (0x1ul << PM_APBCMASK_AC1_Pos)
#define PM_APBCMASK_TCC3_Pos 24 /**< \brief (PM_APBCMASK) TCC3 APB Clock Enable */
#define PM_APBCMASK_TCC3 (0x1ul << PM_APBCMASK_TCC3_Pos)
Finally I added in gclk.h (component) in line 150:
#define GCLK_CLKCTRL_ID_TCC3_Val 0x25ul /**< \brief (GCLK_CLKCTRL) TCC3 */
and in line 188:
#define GCLK_CLKCTRL_ID_TCC3 (GCLK_CLKCTRL_ID_TCC3_Val << GCLK_CLKCTRL_ID_Pos)
So here is my (untested) Code, can someone with more knowledge than me plz check and test it accordingly?
Edit: in the pio-file #DEFINE has of course to be replaced with #define (lower case). Uploaded corrected Code.
Hello: You have tried TCC3 in this way, does it work? I would need the TCC3 on the ATSAMD21G18A but I think it is only available on the ATSAMD21X17D according to Configuration Summary Table 2-1 in the datasheet, since it is the only one that has 4 TCC (TTC0, TCC1, TCC2 and TCC3)
Hey, I'm getting an PWM Output from the pins, so either I have coded something else wrong or this is working. I can't tell for sure, as I do not see myself qualified enough to test it thoroughly. Also, table 7-1 states TCC3 for SAMD21E, SAMD21G and SAMD21J devices. If you have time to test it, I'd be happy to receive feedback.
Hey, there is a bad news based on the DS40001882F datasheet for SAM D21/DA1 Family, "Table 2-1. SAM D21 E/G/J and SAM D21 EL/GL Product Family Features" shows the only device groups support 4 TCC are ATSAMD21x17D or ATSAMD21x17L. ATSAMD21G18A supports 3 only, 0-3. I spent couple of days to try to make it work, but I wasn't able to turn on the clock REG_PM_APBCMASK for TCC3.
Hey, there is a bad news based on the DS40001882F datasheet for SAM D21/DA1 Family, "Table 2-1. SAM D21 E/G/J and SAM D21 EL/GL Product Family Features" shows the only device groups support 4 TCC are ATSAMD21x17D or ATSAMD21x17L. ATSAMD21G18A supports 3 only, 0-3. I spent couple of days to try to make it work, but I wasn't able to turn on the clock REG_PM_APBCMASK for TCC3.
Ok, thx for testing; I must have done something else wrong then to get a PWM-like output there. Probably the addressing makes the Pins turn on and off by accident when accessing the power manager or something. I think you can close the issue then.