SDRAM.h uses PLL2 instead of HCLK3 (same freq on Portenta)

[Bexin3]

Hello, It seems ram_internal.c and .h / SDRAM init uses and fully defines PLL2, leaving one with no configurable clocks if using a display. This seems pointless on Portenta, as using HCLK would result in same 200mhz for the FMC clock, while on giga it's 240mhz, which is a slightly higher, but it gets divided by two into 120, staying within the spec of 166mhz. Further in my pull request for giga I changed the frequency defined, and I believe based on this timings get automatically calculated to ensure the correct delays, Not having PLL2 available is a huge limited on projects.

[Bexin3]

After checking again, it is already divided so it would be running at 120mhz still within spec, I have now opened a pull request https://github.com/arduino/ArduinoCore-mbed/pull/995 to change this