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An experiment for building gateware for the axiom micro / beta using amaranth-hdl
This adds a verify method to the `axi_writer_demo.py` to find errors in the `DramPacketRingBufferStreamWriter` implementation.
There are some additional things that should go into the cache key: 1. clock constraints 2. `NMIGEN_*` environment variables 3. maybe the `nmigen`, `nmigen-boards`, `...` version
To simplify code and reduce the possibility for bugs, we want to rework the way addresses and the memorymap works. 1. Addresses should be in units of the bus word...
This adds a remapper, that reorders the pixels coming from the cmv12k to follow the `ImageStream` convention, though notably with more than a single pixel per cycle. Untested in hw,...