[SVE] Implement scalable vectors in TVM

[ekalda]

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This prototype is to accompany the open SVE RFC. It implements the design outlined in the RFC.

The main changes to the stack include:

1. tir.split can accept an expression with vscale as a factor

2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes

3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer

4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile ~and TVMScript parser support for predicates~.

[cbalint13]

1. tir.split can accept an expression with vscale as a factor
2. LoopVectorizer can create Ramp and Broadcast nodes with scalable lanes
3. BufferLoad and BufferStore nodes can accept an optional predicate which is created in LoopVectorizer
4. LLVM codegen can lower the scalable predicated vectors into llvm.masked.* intrinsics

The prototype is currently missing tir.tile and TVMScript parser support for predicates.

Hi @ekalda ,

Very nice work !

I can't comment much, I think this implementation is a careful step toward SVE. Will test this on some RVV CPU implementation to see a walk through the LLVM masked.* things.

[ekalda]

@tvm-bot rerun