[TIR][Schedule] Relax cache read/write's restriction and fix unexpected behavior

[multiverstack-intellif]

trafficstars

Currently, cache read/write requires to be stage pipeline, but it is unnecessary theoretically. When there is WAR, the target of cache_read could be specified by the consumer_blocks parameter. This also allows cache_write to handle the write after read of the same buffer.

cc @Hzfengsy @junrushao1994 @wrongtest-intellif