Aleš Katona

Thanks for the data, I'll try and get to this before the next release.

Seems this is an android/arm specific issue on chips that support putting cores to sleep fully. Mentioned in [on stack overflow here](https://stackoverflow.com/questions/22405403/android-cpu-cores-reported-in-proc-stat) I need to find out how it behaves...

I've made a pre-release version which should contain a fix for this problem [here](https://github.com/almindor/lighthouse/releases/download/v1.6.5-sleepfix/harbour-lighthouse-1.6.5-1.armv7hl.rpm). Can you please try and install that rpm and see if it works? The sha256 is...

> I haven't spoken to the @rust-embedded/riscv team yet but if they're interested in the riscv32i-unknown-none-elf, riscv32imac-unknown-none-elf, riscv32imc-unknown-none-elf, riscv64gc-unknown-none-elf, riscv64imac-unknown-none-elf, or riscv32im-unknown-none-elf targets I'm happy to add them to the...

> FYI the `riscv-rust-quickstart` link 404s, I guess the link should be https://github.com/riscv-rust/riscv-rust-quickstart, but this seems to be a quickstart for the discontinued hifive boards. It might make sense to...

> @romancardenas, @almindor, would you mind checking the [proposed rv32 file](https://github.com/adamgreig/rust/blob/target-support-rewg/src/doc/rustc/src/platform-support/riscv32imac_unknown_none_elf.md)? In particular > > > * I've combined i, imc, and imac into one file, as they're all tier...

This is an interesting take. I agree that `std` vs `core` is something that should've been handled better. Sadly the cat is out of the bag now and getting a...

`cargo-nono` seems like a good first step. One issue I think still remains is the "core std" false equivalency. I'm sure there are cases where `core::something` does not equal to...

Is something still blocking this? AFAICS all the PRs are merged?

I think this is a good approach once it's clean and tested. I only had time to skim through it but don't see anything "wrong" with it.