agrobman

thanks Olof and Jan for explanation, BTW, FTDI chip has two serial channels can be configured as JTAG IFs, Can the 2nd one be connected/used as original swerv JTAG interface...

thanks Olof, this diagram is really good. A few more wishes: 1) user_rst - what is its source? where it come from? How is it related to the board "reset"...

or solder these two pins to some FPGA IO/connector (QFP package pins are exposed to soldering ...) Oh, they actually confirmed that we CAN connect/solder these pins with wires to...

the 2nd option is questionable. a) there is no TRST line in their adapter/pin connector. b) Not sure if we can connect/use the FPGA JTAG pins to/in our design directly,...

I meant to use FPGA TDI/TDO/TCK/TMS pins as SweRV JTAG pins. Does Vivado allow to reuse these pins for emulated design? Regarding adapters - I couldn't find one which can...

Jan, BTW, did you ever use/check original SwerV DMI module in FPGA emulation with any debugger?

use 'verilator' instead of 'irun' with make command or whatever system verilog simulator you have of the supported by the project makefile (vcs, vlog etc) (read README.md first, how to...

got the same problem today. Solved this with the same include independently before seeing this ticket. @timsifive , could you, please, just add this include in the file? Not sure...

I can’t , I have other changes in my files Alex

I was thinking creation and than using a library (archive) may reduce memory demand during linking in expense of compilation time (?). where should I place the clock_gater comment ?...