Adam Greig

This is #312; previously the implementation was broken on Cortex-M7 cores (#236) where it would complete in fewer than the requested number of cycles, whereas now it always takes at...

Hm, that's annoying, we deliberately double the number of cycles `delay()` blocks for in #312 to accommodate the dual issue pipeline of the Cortex-M7 (#236); in fact this led to...

From the lack of comments I guess this isn't too objectionable to anyone! I don't think the 24 byte flash overhead is a huge price to pay as-is, and definitely...

Currently this repository is designed to be used with `cargo generate`, which means there are a bunch of placeholder values which are not valid if you just copy the repository...

bors r=newAM

I like putting it in the pin list string(s), it's compact but I think also quite clear. Maybe "~A1" would be a better match to the nmigen negation syntax?

Looking at some DSP I wrote in nmigen, I actually use slicing more frequently to select the msbits of some signals than the lsbits, i.e. I'm doing `msbits = x[16:]`...

> the payload staying the same while valid is asserted and until ready is asserted what's the motivation for this constraint? I've found [this post](http://fpgacpu.ca/fpga/handshake.html) about ready/valid signals to be...

Closing this as no longer relevant now we've got rid of all the pre-compiled blobs.

I'm still seeing it as open, but it certainly shouldn't be closed yet, you're right. Now that we have cfg_global_asm being used with features like set-vtor and set-sp, and soon...