Adam Greig

Thanks for trying to get it working! The error message is saying that the SMS1 field in the TIM1_SMCR register has some `enumeratedValues` provided by ST, including one with a...

Urgh, I think this issue affects almost every STM32 file we have. The only ones that don't seem affected are the G4 and L0 and L1 families; every other chip...

The CubeMX data is also available here: https://github.com/stm32-rs/cube-MX-db I think it would be a _lot_ of work to get a meaningful amount of AF entries encoded compared to what we...

I guess the L412 didn't exist at the time; we say that the L4x2 crate [supports L432/42/52/62](https://github.com/stm32-rs/stm32-rs/blob/master/stm32_part_table.yaml#L483-L492) but not 12. Perhaps ST have released a new SVD file for the...

Unfortunately it looks like ST issue the same `STL32L4x2` SVD file for the L412, which evidently isn't quite correct for it. That said, it's pretty common for devices to be...

> And there is considerable implementation and maintenance overhead involved with implementing both ways, since then we have to think about how to make all the peripherals play nicely with...

> This would configure the device correctly, but would be unsound, leaving race conditions. Sorry, I don't think I was clear: we provide two configuration methods, one of which internally...

@IamfromSpace Good catch, you're quite right, we can't allow simultaneous use of "pass in the &mut" and "we'll create one in an unsafe block". Your ShareableRCC idea sounds a lot...

In the ARMv7-M architecture reference manual, A3.4.5 "Load-Exclusive and Store-Exclusive usage restrictions", it says: > LDREX and STREX operations must be performed only on memory with the Normal memory attribute....

Thanks for the PR and your other recent G4 work! The failures are coming from the linter which checks the generated SVD complies with the CMSIS-SVD schema: if you run...