What platform-specific optimizations does Abseil do?

[MaxiBoether]

Hello!

In the header optimization.h, we define various macros, such as the cache line size on PowerPC, ARM, and x86. However, I could not find a use of these values in the containers. Especially, I am interested in how much architecture-specific optimizations on the hash table containers are done, with respect to cache line size, memory layout (sequential vs random) as well as other possible optimizations (e.g., specific instructions or such things).

If this is documented somewhere, I am sorry for asking, and would be glad for a pointer. I could not find that in the code, other than the optimization.h file.

Thank you so much!

Best, Maximilian

[derekmauro]

optimization.h isn't particularly relevant to understanding Abseil's hash tables. Here are some better resources:

https://abseil.io/about/design/swisstables https://www.youtube.com/watch?v=ncHmEUmJZf4

[MaxiBoether]

Thanks for the pointers! I have already read the swisstable design document you linked, and I will watch the talk you sent. However, I was rather referring to platform-/architecture-specific optimizations, not the general design, i.e., choices like data alignment for specific platforms (for example that ARM's HBM heavily prefers sequential access), not to the general data structure and algorithmic ideas. This is why I was pointing to optimization.h.