CoreLib
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Dictionary
https://github.com/VHDL/CoreLib/blob/efe6954672614326fc41b0dbef8cd9395edc8bd9/data_structures/src/Dictionary.vhd#L108
The package is instrumented up to support different sized std_logic_vectors.
In Set, when a key is found, it is "assumed" to be the same size as the current value.
Is this an ok assumption? Could the set value be a different size?
Uh, it's long time ago, that I wrote this code 😄 Do you mean that the memory, needed for the new value, maybe has to allocated new because the new value has another size? You're right, the assumption that values are of same size is probably not okay.