Goto definition with component in architecture

[nicobld]

When having the component written in the architecture that instantiates it, the goto definition goes to the component in the same file, and the goto implementation doesn't do anything. It is impossible to goto the entity definition of b, I'd expect at least one of the gotos to go there.

a.vhd

library ieee;
use ieee.std_logic_1164.all;

library lib;
use lib.all;

entity a is
begin
end entity;

architecture rtl of a is
  signal p : std_logic;
  component b is
    port (
      p : std_logic
    );
  end component;
begin
  b_inst: b
    port map (
      p => p
    );
end architecture;

b.vhd

library ieee;
use ieee.std_logic_1164.all;

entity b is
  port (
    p : in std_logic
  );
end entity;

vhdl_ls.toml

[libraries]
default.files = [
  'a.vhd'
]

lib.files = [
  'b.vhd'
]