[BUG] File analysis aborted and falsely flagged as missing after prior fatal error

[nselvara]

Bug description:

Hi there,
This issue appears to stem from: https://github.com/VHDL-LS/rust_hdl/issues/254

When encountering a case like the one above, VHDL LS stops analysing the rest of the file or breaks the analysis entirely, and erroneously reports that the unit does not exist or could not be found, displaying: No primary unit 'xy' within library 'acme'.

While it's understandable that the analyser might not recover gracefully from certain semantic issues, I'd suggest (at least for now) simply skipping analysis beyond this point instead of halting completely. This way, other parts of the file can still be processed.

I'm aware this may be a deeper issue, but I wanted to report it nonetheless in case it helps improve robustness.