Selected names from 'unusual' places

[Schottkyc137]

VHDL allows to prefix a name with the label of the enclosing element as 'scope'. For example, for processes:

P: process
    variable DATA: INTEGER;
begin
    -- Within process P, the name "P.DATA" denotes a named entity
    -- declared in process P.
end process;

This example is directly taken from the LRM (8.3; examples)

At the moment, the language server sees this as an error.

The same is likely true for blocks, generate statements and probably more.

[lgu-appear]

I didn't even know this existed in VHDL, but I find it amazing to help readability in code when you have for..generate and block. Would be cool to see this fixed!