Need FPGA device database backend from VPR

[litghost]

The VPR architecture XML and RR graph should be enough information to generate an FPGA interchange device database.

[mkurc-ant]

One of possible challenges I see here is that a VPR rr graph is flattened and the interchange format requires definition of repeatable tiles. There is a need for a mechanism that would analyze a rr graph and identify repeating patterns of nodes and edges.

This is actually done in the OpenFPGA project which use VPR together with "tileable graph" https://openfpga.readthedocs.io/en/master/#. This is exactly what is needed for the interchange.

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