Upstream VTR throws error on buffered switches

[acomodi]

With master+wip and master getting closer, there is one outstanding fix to be done to have an error-free build of Symbyflow tests with upstream VTR.

The error encountered is due to the following code block: https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/b22e1fe54b206ca636081fa8c16bb21929047af6/vpr/src/route/rr_graph_indexed_data.cpp#L369-L394

In particular, VTR throws a fatal error as switches belonging to the same wire segment have different buffered values. This does not happen in the current master+wip, and the code block resposible looks like the following: https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/f1a3bcc2a8aa93d88cb26ca7f1853962fff57c32/vpr/src/route/rr_graph_indexed_data.cpp#L376-L414