System-Verilog Practice

Want to learn System Verilog but don't know where to start ?
Here is the complete System Verilog BootCamp for you. This repository contains System Verilog practice code from basic to advance.

Compiler Setup

• EDA Playground is free web application that allows users to edit, simulate, synthesize, and share their HDL code.
• Select SystemVerilog/Verilog under Testbench + Design tab
• Leave the default settings for OVM/UVM and Other Libraries
• Under Tools and Simulators select Synopsys VCS 2020.03 (If you wish to simulate it in some other simulator, then you can choose that in drop down list box)
• design.sv is to design the actual logic circuit. testbench.sv is to test the design that we have done in design.sv
• Click Run button to Run the code.

Topics

• Data Types
• Control Flow
• Processes
• Communication
• Interface
• Class
• Constraints
• MISC
• Functional Coverage
• Assertion

Syllabus