Kernel/USB: Reorganize UHCI schedule structure

[b14ckcat]

Currently in the UHCI code, when a queued (interrupt/bulk/control) transfer is submitted, it will attach itself to the corresponding queue head which is linked into the schedule for execution by the hardware controller, overwriting any previous transfers that are occupying that memory spot. This means only one transfer of each type can be executed simultaneously, and also opens the door to other problems like memory leaks and transfers that never complete. The first commit fixes this by transforming the schedule as set up by the software into a linked list with sentinel values ("anchors") to insert new transfers in front of as needed, while maintaining the correct transfer type ordering. When a transfer & transfer descriptor chain is created, it is also allocated a queue head to link to it and link into the schedule list. The second commit further prepares the schedule for the implementation of interrupt transfers, which are up next after async transfers. It creates several separate interrupt queue head anchors, each designated a different power-of-two latency between 2^0 and 2^10 milliseconds, to allow for interrupt transfers with different execution periods to be queued up.

[BuggieBot]

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[stale[bot]]

This pull request has been automatically marked as stale because it has not had recent activity. It will be closed in 7 days if no further activity occurs. Thank you for your contributions!

[b14ckcat]

Not stale :)