SebLague
[Bug] Behavior of circuit depends on order of gate placement
In the following circuit:
If the left-most OR gate is placed last, then the circuit behaves as a D flip-flop.
However, if the right-most AND gate is placed last, then the circuit behaves differently, and produces no output.
The expected behavior is for the circuit to behave identically no matter what order the chips are placed in.
See video at https://www.youtube.com/watch?v=l7xTDD1ZFnE
You mean like, if you leave all the connections the same but just drag the left most OR gate all the way to the right so it's the furthest right chip on the board?
You mean like, if you leave all the connections the same but just drag the left most OR gate all the way to the right so it's the furthest right chip on the board?
No it's order of connection to the circuit. Chips can be placed down anywhere but it only matters when you go to wire it up.
Yes, that ^^^
Also, since you mention it, fwiw I don't actually know if it's dependent on order of chip placement or order of wire placement. My only test was to remove then re-add the chips. I didn't try removing then re-adding only the wires while leaving the chips.
Yes, that ^^^
Also, since you mention it, fwiw I don't actually know if it's dependent on order of chip placement or order of wire placement. My only test was to remove then re-add the chips. I didn't try removing then re-adding only the wires while leaving the chips.
Yeah I tried it out after seeing your video and it seemed to be wire dependant but you should test it out too. More data, easier to bugfix
um, I watched the video and the circuit produces a pulse output when both inputs are 1 - you put a pulse generator after an AND gate when the AND gate was produced last.
I've seen the video and have a theory. I could be wrong but I think that the behavior is dependent on the order of updates to the wires. If the signal from the bottom of the and gets updated first, then it behaves like a d-flip flop, while if the signal from the top gets updated first, nothing happens? I think the first behavior might be the more accurate one.
When you turn off the bottom one, that allows a high signal to reach the bottom of the 'and', but also the lowers the output of the first and, thus lowering the top signal of the 'and', and lowering the output, which was already lowered, causing nothing to happen.
I'm going to try it on mine:
Bug still occurs.
I simplified the bug-occurence.
It can also be reproduced via:
After inspecting the source code of the Cycle Detector the cycle flag is naturally set based on the order of gate placements
In the circuit from @Augustin007 :
When the AND gate is placed last the cycle flag is set on the first input pin to the OR gate:
And when the OR gate is placed last the cycle flag is set on the first input pin to the AND gate:
So i think this is a bug with the cycle detector.
The cycle flag stops the chip from propagating the signal until Simulator.Simulate() is called to propagate the signal once (avoids stackoverflow). It's called every frame, so the reason it behaves differently might be because of a delay which is only experienced in one of the scenarios.
