a2o

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Completions eventually get X's when FLOAT_TYPE = 0 (no FPU gen'd).

openpowerwtf

Can the 'entries' parameters be made to work? RTL doesn't compile when changed. ``` RV_FX0_ENTRIES 12 // and FX1, LQ, AXU0, AXU1, UCODE ```

openpowerwtf

Setting works at 16 but not 8 or 4. Are there other dependencies, like CPCRx values or RV settings? ``` `define CPL_Q_DEPTH 16 ```

openpowerwtf

These parameters do pass initial sim. Determine if ```IBUFF_DEPTH=4``` can/should be supported, and document. Also, prefetch enabled with different values should be tested. ``` `define IBUFF_DEPTH 6 //wtf 4 fails...

openpowerwtf

Sim fails on second ifetch. ``` `define INCLUDE_IERAT_BYPASS 0 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) ```

openpowerwtf

Setting DC size to 16K causes some vector size warnings, and fails sim (X's after ~1K cycles). ``` `ifdef DC_32 `define STQ_DATA_SIZE 64 // 64 or 128 Bit store data...

openpowerwtf

These settings compile/elab but hangs in sim (no completions). Need to document dependencies/requirements/etc. and test. ``` `define LDSTQ_ENTRIES 4 // ?order? `define LDSTQ_ENTRIES_ENC 2 `define STQ_ENTRIES 5 `define STQ_ENTRIES_ENC 3...

openpowerwtf

Cleaned up compile/elab errors, but fails with X's after a few I-fetches: ``` `define EXPAND_TLB_TYPE 0 ```

openpowerwtf

UM 14.5.142 ```verilog spr_xucr0_init = 1120 assign spr_xucr0_clkg_ctl = xucr0_q[38:42]; assign spr_xucr0_trace_um = xucr0_q[43:46]; assign xu_lsu_spr_xucr0_mbar_ack = xucr0_q[47]; assign xu_lsu_spr_xucr0_tlbsync = xucr0_q[48]; assign spr_xucr0_cls = xucr0_q[49]; assign xu_lsu_spr_xucr0_aflsta = xucr0_q[50];...

openpowerwtf

If it's a short video described, it's probably better to upload the video file or youtube link directly rather than using Google Drive, also that link `A2O Build Process` is...

kzall0c