open-fpga-verilog-tutorial
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Obijuan
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
Running arachne on counter.v from tutorial 4 (the 26 bit counter) results in a fatal error due to missing set_io constraints. The counter.v file contains: `module counter(input clk, output [25:0]...
Hi Obijuan, first: compliments for your Tutorial. Best Tutorial on Verilog with very nice examples. I have a question on T27-Memoria ROM generica. In genrom.v you use posedge clk to...
I am having problems by charging programs on de Icezum Alhambra. It seems like something is not correct with the drivers because every time I try to charge a code...
Processing icestick (platform: lattice_ice40; board: icestick) ---------------------------------------------------------------------------------------------- Verbose mode can be enabled via `-v, --verbose` option yosys -p "synth_ice40 -blif .pioenvs\icestick\hardware.blif" -q src\countsec.v ERROR: Can't open include file `divider.vh'! ***...
Buenas, Creo este "issue" para comunicar el hecho de que en los makefiles presentes en el tutorial de ICESTICK, la siguiente línea: ``` #-- Compilar iverilog $^ -o $(NAME)_tb.out ```...
Hi Obijuan, First of all, thanks for the awesome tutorial. It is really helping me start my (open-source) journey with FPGAs. I don't know if you would be interested in...
