Support for CTI/CTM for synchronized halt/resume

[haneefdm]

This is an idea to explore. We know it is possible in a multi-core ARM system using CoreSight components to near-simultaneously halt/resume all cores. My own knowledge on this is limited and confusing, so please feel free to comment and correct/educate me.

My sources of information are

1. OpenOCD Section 16.2
2. Cortex-M7 CTI functional description
3. ARM DS-5 Debugger User Guide
4. Linux implementations
5. Analog Devices App Note
6. Intel (Altera) implementation of the same

From what I can tell, each vendor implements it their own way, and there is no set rule for what is CTI channel 0, which CTI is associated with which CPU, etc. Most of them point to ARMs documentation and it just refers to what is possible with actual implementations that are device-specific.

My goal is to implement the synchronized halt/resume via OpenOCD. Yes, others (JLink, STLink) can do it as well but they have proprietary/unpublished interfaces.

I would love to hear experiences with other IDEs like IAR, Keil, SEGGER, etc. on what (guess) happens under the hood.

For OpenOCD, what I was told was

• You pulse a specific device-specific CTI channel to halt all CPUs
• You pulse a different device-specific CTI channel to resume all CPUs

CAVEATS: How do breakpoints work? If a breakpoint occurs in one CPU, should it halt all CPUs? When a breakpoint occurs, it takes SW like ours a looooong time before we find out and sure we can halt all CPUs but is that good enough? Perhaps.

Single stepping is another thought. single-stepping across cores doesn't make sense to me. Also, single-stepping in C-code is a virtual thing, it involves a whole sequence of stepi, halt, and resumes at a lower level.

EDIT: Jun 26 9:26 PM PST According to reference (3) above, it should/will stop all cores if any core hits a breakpoint or watchpoint.