Add missing 'and' instructions in llvm bc of spir/test_atomic_and_local_[u]int (Fix #1319)

[zsrkmyn]

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This PR tries to fix #1319.

The atomics.zip was updated as follows,

unzip atomics.zip
cd atomics
llvm-dis test_atomic_fn.atomic_and_local_{u,}int.bc{32,64}
patch < ../atomics.patch
echo -n test_atomic_fn.atomic_and_local_{u,}int.bc{32,64} | xargs -d' ' -l -i llvm-as {}.ll -o {}
rm *.ll
cd ..
zip -u -r atomics.zip atomics/

The atomics.patch above is as follows,

--- test_atomic_fn.atomic_and_local_int.bc32.ll 2021-09-09 16:27:15.797881663 +0800
+++ test_atomic_fn.atomic_and_local_int.bc32.ll 2021-09-09 16:27:54.094463292 +0800
@@ -15,7 +15,8 @@
   tail call spir_func void @_Z7barrierj(i32 1) #0
   %7 = shl i32 %3, 5
   %8 = sub i32 %1, %7
-  %9 = shl i32 1, %8
+  %shl.mask = and i32 %8, 31
+  %9 = shl i32 1, %shl.mask
   %10 = xor i32 %9, -1
   %11 = tail call spir_func i32 @_Z10atomic_andPVU3AS3ii(i32 addrspace(3)* %Local, i32 %10) #0
   tail call spir_func void @_Z7barrierj(i32 1) #0
--- test_atomic_fn.atomic_and_local_int.bc64.ll 2021-09-09 16:27:15.800881944 +0800
+++ test_atomic_fn.atomic_and_local_int.bc64.ll 2021-09-09 16:28:21.254003347 +0800
@@ -22,7 +22,8 @@
   %10 = shl i64 %3, 5
   %11 = sub i64 %4, %10
   %12 = trunc i64 %11 to i32
-  %13 = shl i32 1, %12
+  %shl.mask = and i32 %12, 31
+  %13 = shl i32 1, %shl.mask
   %14 = xor i32 %13, -1
   %15 = tail call spir_func i32 @_Z10atomic_andPVU3AS3ii(i32 addrspace(3)* %Local, i32 %14) #0
   tail call spir_func void @_Z7barrierj(i32 1) #0
--- test_atomic_fn.atomic_and_local_uint.bc32.ll        2021-09-09 16:27:15.802882131 +0800
+++ test_atomic_fn.atomic_and_local_uint.bc32.ll        2021-09-09 16:28:36.846461608 +0800
@@ -15,7 +15,8 @@
   tail call spir_func void @_Z7barrierj(i32 1) #0
   %7 = shl i32 %3, 5
   %8 = sub i32 %1, %7
-  %9 = shl i32 1, %8
+  %shl.mask = and i32 %8, 31
+  %9 = shl i32 1, %shl.mask
   %10 = xor i32 %9, -1
   %11 = tail call spir_func i32 @_Z10atomic_andPVU3AS3jj(i32 addrspace(3)* %Local, i32 %10) #0
   tail call spir_func void @_Z7barrierj(i32 1) #0
--- test_atomic_fn.atomic_and_local_uint.bc64.ll        2021-09-09 16:27:15.805882411 +0800
+++ test_atomic_fn.atomic_and_local_uint.bc64.ll        2021-09-09 16:28:50.301719992 +0800
@@ -22,7 +22,8 @@
   %10 = shl i64 %3, 5
   %11 = sub i64 %4, %10
   %12 = trunc i64 %11 to i32
-  %13 = shl i32 1, %12
+  %shl.mask = and i32 %12, 31
+  %13 = shl i32 1, %shl.mask
   %14 = xor i32 %13, -1
   %15 = tail call spir_func i32 @_Z10atomic_andPVU3AS3jj(i32 addrspace(3)* %Local, i32 %14) #0
   tail call spir_func void @_Z7barrierj(i32 1) #0

[zsrkmyn]

ping

[zsrkmyn]

ping

[kpet]

Closing and re-opening the PR to retrigger the CI.

@EwanC @alycm This one touches the SPIR tests. You may want to take a look at it assuming you still have an interest in the corresponding extension.

[CLAassistant]

All committers have signed the CLA.