Jacek Wieczorek

### hdllang - [x] #192 - [ ] `all(...)`, `any(...)` builtins equivalent to `fold_and(join(...))` and `fold_or(join(...))` respectively but all arguments must be `wire`. This will be helpful when writing long...

### Feature description As in the title

### Feature description as above

Treat `iverilog` warnings as errors for SV codegen output testing

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`iverilog` does not have `-Werror` switch so this will likely require some "grepping" on Rust side.

General generic-related error reporting improvements

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### Feature description I know this is probably a big one (but not sure), but it would be nice if the compiler could print values of relevant generic variables when...

### Feature description If an entire signal is bound directly to module instance interface, there's no need to create an additional intermediate signal. In case of registers we want to...

### Feature description It's supported in bindings anyway. Make sure it works in declarations as well. ```sv module X {} impl X { const wire x[10]; const ubus y[10] =...

### Feature description Currently, `default` is allowed at any place inside the `cond` expression. This may be counterintuitive in practice, because other conditions are checked top-to-bottom. Perhaps we should enforce...

### Feature description Builtin function evaluation needs to be implemented. This is needed for code such as: ```sv module X {} impl X { const ubus x = 0; const...