Defer sensitivity deduction to generic module instantiation / add support for sensitivity deduction in generic-dependent branches

[Jacajack]

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Input

module big_or {
	int WIDTH;
	int NUM_INPUTS;

	input clock clk;
	input comb(clk) ubus<WIDTH> inputs[NUM_INPUTS];
	output comb(clk) ubus<WIDTH> out;
}

impl big_or {
	// Assert NUM_INPUTS is positive
	const ubus<(NUM_INPUTS > 0 ? 1 : 0)> assert_num_inputs_positive = 1;

	if (NUM_INPUTS == 1) {
		out = inputs[0];
	}
	else if (NUM_INPUTS == 2) {
		out = inputs[0] | inputs[1];
	}
	else {
		ubus<WIDTH> left_in[NUM_INPUTS / 2]; // FIXME temp signal
		ubus<WIDTH> right_in[NUM_INPUTS - NUM_INPUTS / 2];

		for (i in [0:<NUM_INPUTS / 2]) {
			left_in[i] = inputs[i];
		}

		for (i in [0:<NUM_INPUTS - NUM_INPUTS / 2]) {
			right_in[i] = inputs[i + NUM_INPUTS / 2];
		}

		ubus<WIDTH> left_out;
		big_or left {
			WIDTH,
			NUM_INPUTS: NUM_INPUTS / 2,
			clk,
			inputs: left_in,
			out: left_out
		}

		ubus<WIDTH> right_out;
		big_or right {
			WIDTH,
			NUM_INPUTS: NUM_INPUTS - NUM_INPUTS / 2,
			clk,
			inputs: right_in,
			out: right_out
		}

		out = left_out | right_out;
	}
}


module big_or_16 {
	input clock clk;
	input comb(clk) ubus<16> inputs[16];
	output comb(clk) ubus<16> out;
}

impl big_or_16 {
	// COMMENT THIS OUT TO MAKE IT WORK
	big_or b {
		WIDTH: 16,
		NUM_INPUTS: 16,
		clk,
		inputs,
		out
	}
}

Output

Error: 
  × This signal is missing a sensitivity qualifier
    ╭─[tests/input/074_big_or.hirl:20:1]
 20 │     else {
 21 │         ubus<WIDTH> left_in[NUM_INPUTS / 2]; // FIXME temp signal
    ·                     ───────────┬───────────
    ·                                ╰── Signal must be either const, clock, comb, sync or async
 22 │         ubus<WIDTH> right_in[NUM_INPUTS - NUM_INPUTS / 2];
    ╰────
  help: Please add sensitivity qualifier to this signal.

Expected

The sensitivity should be deduced from inputs array. This error only happens when the module is instantiated