Nice to have features

[Jacajack]

hdllang

• [x] #192
• [ ] all(...), any(...) builtins equivalent to fold_and(join(...)) and fold_or(join(...)) respectively but all arguments must be wire. This will be helpful when writing long conditions
• [ ] Internal improvment: represent registers and module instances the same way internally
• [ ] Ban mixed wire/bus logic & arithmetic. Add to_wire() builtin for bus -> wire conversion and to_bus() for wire -> ubus<1> conversion. This should eliminate strange signedness deductions to unsigned when wire is used in an expression along with buses. (see test case 037_propagate_signedness.hirl)
• [ ] msb(bus<N>), msb(bus<N>, int) builtins which select a certain number of most significant bits from an expression (analogous to trunc()). Perhaps lsb() could be an alias for trunc().

SV Codegen

• [ ] generate block names
• [ ] always_comb for assignments
• [ ] always_ff for registers

global

• [ ] unused keyword
  • [x] #303
• [x] #225
  • [x] sbus and ubus would be really helpful and nicer than having to type unsigned/signed
  • [x] reg instead of register (also covers 1 SV keyword)
• [x] referencing register output via it's name (equivalent of register_name.data)
• [ ] #419
• [ ] assertions (two types: as statements and expressions)

  // statement form:
  assert(x == 0);
  
  // embedded in expression (must have conditionals to make sense):
  wire x = (y == 0) ? z : (y ==1) ? w : unreachable("message"); 
  // should result in following SV assertion being generated
  assert(!(y == 1) && !(y == 0));
  

• [ ] ban clock operations
• [ ] signal matrix operations (a big one)