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Published 20 hours ago • verified publisher icon FPGAwars

Update testbench generator

Open Jesus89 opened this issue 7 years ago • 1 comments
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To be compatible with Icarus Verilog v10_2 (toolchain-iverilog v1.2.0)

Related to https://github.com/FPGAwars/icestudio/issues/209

Jesus89 avatar May 17 '18 23:05 Jesus89

Noticed that vvp, in linux diatribution at least, is dinamicaly linked in previous release. Main binary was fine.

mmicko avatar May 20 '18 14:05 mmicko