Digital-Logic-Sim-CE
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1Hz clock forgets its connections when compiled
I made a simple togglable clock by sticking an input line and a 1Hz clock into an AND, which works until it is saved and exported. The new clock chip then does nothing. Right clicking it and viewing it shows me that the wire connecting the clock to the gate has vanished, and I think the input line becomes bugged too.
This is with 0.39.1 x86 64bit on Windows.
Demo of the chip before saving:


Compiled chip not working (just take my word that it isn't toggling on/off here obviously its hard to demo without video):

Clearing that and then going to view the "TOGGLE CLOCK" chip:
connection vanished:

and finally, the input wire being bugged:

This actually happens with any chips that do not have both an input AND an output. It has been an issue since the previous version